Efficient Test Data Compression Techniques using Viterbi Architecture

P. N. V. A. Swetha, P. M. Francis, B. Prasad Kumar

Abstract: This paper presents the long data compression and the Cmos transistor count increased new fault technologies theses data compression the large data compression and storing the data are described, for provides high encoding efficiency and scalability with respect to the number of test channels support test channel the support algorithm is Viterbi-based test compression. Instead of using the linear equation, the viterbi algorithm proposed scheme finds a set of compressed test vectors very rapidly. According to cost function the branch metric of the Viterbi algorithm, an optimal compressed vector is selected among the possible solution set. By this algorithm we are deriving the condition such as low-power compression and improving capability to repeat test patterns. The proposed on chip de compressor follows the structure of Viterbi encoders which require only one input channel. Experimental results on test volume propose the scheme also yields efficient power-dissipation/volume tradeoff

Keywords: Logic test, low-power test, on-chip decompressor, scalability, test data compression