Area Efficient Full Adder Design for Low Power Application

Karthika .P. S, Sowmiya .J, Brunda Kaleeswari .K, Murlidharan .K

Abstract: In this paper, hybrid logic style is adopted to design the full adder. The main objective of this design is to achieve low power and high speed. Hybrid logic style used is the combination of C-CMOS logic (Complementary Metal Oxide Semiconductor) and Transmission gate (TG) logic. The circuit was implemented using Microwind tool in 90nm technology. Performance metrics of power and speed are compared with existing adder designs such as conventional CMOS adder, Transmission gate adder (TGA). Average Power consumption of the proposed design is found to be 0.265 ?W at 90nm for 1.2V supply.. Delay in the signal propagation is measured as 0.008ns.

Keywords: CMOS, VLSI, Adder, Transmission Gate Adder, Conventional CMOS Adder.