Energy Efficient Floating-Point Based Block LU Decomposition on Large Signal Systems

Anu Philip, Dr. M. Devaraju

Abstract: In this paper, we propose an architecture for floating-point based Lower Upper decomposition of large signal in FPGAs which are dealing with large-sized matrices. Our proposed architecture is based on the well known concept of pipelined floating-point units and the double-precision based design helps to obtain effective throughput. According to the post layout report, the hardware ef?ciency is as high as 1.6? compared with the existing LUD methods, and the energy ef?ciency is also higher than the state-of-the-art LUD when the matrix dimension is 8?8 and larger.

Keywords: Energy ef?ciency, hardware compatability, lower?upper decomposition (LUD), large signal system based FPGAs.