Area-Delay Efficient Modified Majority Gate Binary Adders in Quantum-Dot Cellular Automata

S. Preetha

Abstract: As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The QCA approach represents one of the possible solutions in overcoming this physical limit.Quantum-dot cellular automata (QCA) is considered as an advanced technology compared to complimentary metal-oxide-semiconductor (CMOS) due to QCA-s merits. Many logical circuits are designed using QCA which consume low power. Adders are the basic building block of digital circuits. Initially transistors are used to implement the circuits in digital systems. Nanotechnology is the better alternative to these problems. So in this project I use Quantum-dot Cellular Automata which is an emerging nanotechnology. This technology has the potential for faster speed, smaller size and lower power consumption. In Existing System, an adder is designed which runs in RCA Fasion. In this paper, I propose a new adder design by reducing majority gate and implementing this in the CLA adder. Thus, the reduction of majority gates in the proposed system causes low complexity compared to that of existing system which also causes area and power reduction of about 20% than the existing adder.

Keywords: Adders, majority gate (MG), Verilog HDL, quantum-dot cellular automata (QCA).