Design of Area-Delay-Power Efficient Adaptive Filter using Wallace Tree Multiplier

Sudha .S .A; Dr. Marimuthu C.N

Abstract: In this paper; the fir filter is proposed an efficient multiplication stage technique. To investigate the area; speed; power trade-offs for implementation of FIR filters using MCM and digit-serial arithmetic. Multiple constant multiplications (MCM) are an efficient way of implementing several constant multiplications with the same input data.The coefficients of multiplier are expressed using shifts; adders; and subtractions. To introduce the Wallace tree multiplier for reduce both the number of adders and subtractions as well as the number of shifts.This method can be used to reduce the amount of embedded multipliers in large MCM blocks. We use Xilinx 14.5 to provide VHDL coding for our architecture. Result shows the better performance rate of our proposed work than existing algorithms.This paper is used to reduce the delay product andreduce the area and power consumption in FIR filtering.

Keywords: Multiple constant multiplication; Wallace tree architecture; RPAG algorithm; FIR filter;Pipelining; Partial product generation; Adder depth