Ground Bounce Noise Reduction Using Power Gating Techniques

Lekshmi Vijayan; Sukanya Sundaresh

Abstract: Any computational circuit is incomplete without an adder. The adder cells commonly consume less power and offers high speed. There are several techniques to reduce leakage power and ground bounce noise. This work makes use of power gating techniques in CMOS technology to reduce leakage power and ground bounce noise in mobile applications. It can be mainly divided into two types such as fine-grained power gating and coarse-grained power gating. In fine-grained power gating area consumption is increased due to large number of sleep transistors. In this project coarse-grained power gating technique is used to overcome this problem. In this design, sleep transistors are used as switches to shut off power supplies to parts of a design in standby mode. A sleep transistor is referred to either a high threshold voltage pMOS or nMOS transistors. The sizing of transistors plays a key role in the static CMOS style. Here the conventional CMOS 28 transistor adder is considered as base case. This work also aims to design an ALU circuit using power gating technique. The ground bounce noise and leakage power are analyzed for a conventional CMOS full adder and an ALU circuit. The major performance criteria considered in this design are standby leakage power, ground bounce noise, and area. The simulations are performed by using DSCH2 and MICROWIND2 with different CMOS technologies.

Keywords: Sleep Transistor, Power Gating, Ground Bounce Noise