Efficient Fault Detection Majority Logic Correction with in Memory with Difference-Set Codes

N. V. P. Naidu Babu, P. M. Francis, B. Prasad Kumar

Abstract: Now a-days on soc applications the major problem is with the on chip memory to be faster and we require without any error correction and disrupt the altering digital circuit are becoming the major concern for memory application. This paper presents an error-detection method for difference-set cyclic codes with majority logic decoding. To correct a large no of correction Majority logic decodable codes are suitable for memory applications. However, they require a large decoding time that impacts memory performance. The proposed fault-detection method significantly reduces memory access time when there is no error in the data read. The technique uses the majority logic decoder itself to detect failures, which makes the area overhead minimal and keeps the extra power consumption low.

Keywords: Block codes, difference-set, error correction codes (ECCs), low-density parity check (LDPC), majority logic, memory