Low-Error Vector compensation and correction of Dual Group Input Vector and Hardware-Efficiency Using Fixed-Width Multiplier

Rayala Mahesh, P. M. Francis, B. Prasad Kumar

Abstract: In this paper, we describe a new novel algorithm for design of low power an hardware efficient error compensation circuit by using the dual group minor input correction vector to lower input correction vector compensation error. The on chip soc applications increases the capacity of data transfer that can be utilizing the symmetric property of the minor input correction vector, and complex hardware of the error compensation circuit can be lowered. The error compensation circuit mainly from the ?outer? partial products, the hardware complexity only increases slightly as the multiplier input bits increase. By the utilization of LSB techniques In the proposed 16 X 16 bits fixed-width multiplier, the truncation error can be lowered by 87% as compared with the direct-truncated multiplier and the transistor count can be reduced by 47% as compared with the full-length multiplier. With the help of fixed-width multiplier performs not only with lower compensation error but also with lower hardware complexity, especially as multiplier input bits increase.

Keywords: Fixed-width multiplier, hardware-efficient, low-error