Design of a Multi-Standard DUC Based FIR Filter Using VLSI Architecture

G. Swathi, M. Revathy

Abstract: In Digital Signal Processing FIR Filter is used to remove the noise or unwanted components from a signal. This paper Presents an efficient VLSI Architecture of a Multi-Standard Digital Up Converter (DUC) based FIR filter that is used to remove the noise in the received channel data bits effectively. The proposed DUC based FIR filter consists of weight update block with Shift add architecture to achieve a lower adaptation delay and efficient area, power, delay. In this proposed architecture for achieving an efficient adaptation delay and area-delay-power implementation, shift add architecture is used and to modify the architecture for the implementation of a delayed least mean square (LMS) adaptive filter using three co-efficient inputs. Number of Look Up Table (LUT) counts, path delay time and power consumption are reduced and the results prove that the Proposed technique produces higher speed when compared to the existing DUC based FIR filter architecture.

Keywords: Finite Impulse Response (FIR) Interpolation filter, Digital Up Converter (DUC), Shift add architecture, Partial Product Generator (PPG).