International Journal of Scientific Engineering and Research (IJSER)
Call for Papers | Fully Refereed | Open Access | Double Blind Peer Reviewed | ISSN: 2347-3878


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India | Electronics and Communication Engineering | Volume 5 Issue 3, March 2017 | Pages: 67 - 70


Design of Self Calibrated DLL Based Clock Generator Using Modified GDI Technique

C. Naveena, S. Purushothaman

Abstract: Abstract: This paper describes a low-jitter delay-locked loop (DLL)-based clock generator for dynamic frequency scaling in the extendable instruction set computing (EISC) processor. The DLL-based clock generator provides the system clock with frequencies of the reference clock, according to the workload of the EISC processor. The proposed self-calibration method and a phase detector with an auxiliary charge pump can effectively reduce the delay mismatch between delay cells in the voltage-controlled delay line and the static phase offset due to the current mismatch in the charge pump, respectively. The self-calibrated output waveform exhibits 9.7 ps of RMS jitter and 73.7 ps of peak-to-peak jitter at 120 MHz. The prototype clock generator implemented in CMOS process occupies an active area of 0.25 ?m and consumes power.

Keywords: Calibration, dynamic frequency scaling (DFS), delay-locked loop (DLL), extendable instruction set computing (EISC).



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