Linear Congruential Generator for LUT-SR Architecture

Mary Evanchalin .S; Arulmozhi .P

Abstract: A random number generator (RNG) is a device designed to generate a sequence of numbers or symbols that don?t have any pattern. Hardware-based systems for random number generation are widely used, but often fall short of this goal, albeit they may meet some of the statistical tests for randomness for ensuring that they do not have any ?de-cod able? patterns. In the existing work, they proposed LUTs as shift registers to achieve high quality and long periods, while requiring very few resources. In defining the LUT-SR generators, the provision of a serial load chain is explicitly taken into account, by embedding a chosen cycle into the matrix A from the start. Specifically, we embed a very simple cycle of the form i ? (i + 1)mod r through the XOR bits. In the enhancement work, we proposed enhanced LUT ? SR architecture with a Linear Congruential Generator (LCG) represents one of the oldest and best known pseudorandom number generator algorithms. The theory behind them is easy to understand, and they are easily implemented and fast. Experimental result shows performance level of our proposed architecture. In this, we implement our architecture in VLSI platform. Here our design was made by VHDL programming language by using Xilinx software.

Keywords: Linear Congruential Generator, field-programmable gate array (FPGA), uniform random number generator (RNG)