Efficient Logarithmic Multiplier by Iterative Mitchell's Algorithm Implemented in Verilog

Charan Kumar G., Satya Narayana S., Seren Anish P., Shafath Abdul Nabi K. M., Dr. S. Rajasekharan

Abstract: Multiplication is a basic arithmetic operation. Multiplication operations such as Fast Fourier Transforms, Multiplication and accumulation units, Convolution are some of the computation-intensive arithmetic functions often encountered in Digital Signal processing applications. Generally, Logarithm based multipliers are used in these cases which introduce certain errors. These errors are approximated by various methods. In this paper a simple architecture of a 16X16 logarithm based multiplier is proposed which uses simple combinational and sequential circuits to obtain an exact product. The multiplier has an arbitrary execution time which varies from 0 clock cycles to 15 clock cycles (neglecting the combinational delay) and whose mean delay is 7.5 clock cycles. This architecture is designed and simulated in ?ModelSim? simulation tool.

Keywords: logarithmic multiplication, mitchell's algorithm