Design and Performance Analysis of CNTFET Based Asymmetric Threshold Stacked Leakage Reduction Technique for NVSRAM Cells

Uma Maheshwar Janniekode, Rajendra Prasad Somineni

Abstract: The Asymmetric Threshold and Stacking (AT S) technique has already proved effective for leakage mitigation in CMOS memories. In this work we extend and quantify its impact on Carbon Nanotube Field Effect Transistor (CNTFET) implementations of Non Volatile SRAM (NVSRAM), including a recently reported 8T3R NVSRAM cell. Standard 6T/8T NVSRAMs and the 8T3R architecture were modelled in a 16?nm CNTFET process and benchmarked, under identical bias and workload conditions, against functionally equivalent 16?nm CMOS designs. All circuits were simulated with Synopsys HSPICE. Applying AT S to CNTFET NVSRAMs yielded up to 69?% average leakage power reduction and a 60?% drop for the high performance 8T3R cell, while preserving read/write delay and static noise margin. Relative to their CMOS counterparts, CNTFET based AT S cells delivered an additional ?10?% leakage saving and superior process voltage temperature robustness. These results demonstrate that (i) the AT S technique remains highly effective when ported from CMOS to emerging CNTFET technology, and (ii) CNTFET devices further amplify the power efficiency gains, making the combined solution a compelling candidate for next generation low power, high speed non volatile memories.

Keywords: CMOS, SRAM, NVSRAM NVM, CNTFET, HSPICE, ReRAM